1. Field of the Invention
The present invention relates to a DMA (Direct Memory Access) circuit which directly accesses memory according to an external instruction and transfers data, and a disk array device using this, and more particularly to a DMA circuit which is suitable for guaranteeing the validity of the data on a disk array device to be used as an external storage device of a computer, and a disk array device using this.
2. Description of the Related Art
As various data are computerized and handled by computers, efficiently transferring a large volume of data independently from the computer is now demanded. For this, a technology to independently access the memory to store data according to an external instruction and transfer data, that is DMA (Direct Memory Access) transfer, is actively used.
In the case of a disk array device which can safely store a large volume of data, the large volume of data is read or written by access of the host computer, so the data of the memory is transferred to the host computer or internal circuit.
FIG. 9 and FIG. 10 are diagrams depicting prior art. As FIG. 9 shows, the CPU 100 writes data to the cache memory 104, the DMA circuit (engine) 102 reads the write data in the cache memory 104 and transfers it. When the CPU 100 receives the data from the external device, such as a host, the CPU 100 creates a descriptor and writes it in the control area (descriptor area) 106 created in the cache memory 104.
The descriptor is an instruction for the CPU 100 to send to the DMA engine 102, and includes the address and number of bytes of the transfer data in the cache memory 104, and address of the data transfer destination (memory). For example, as the format of the descriptor in FIG. 10 shows, the descriptor is comprised of a four word (1 word, 64 bits) command. The first word is comprised of the command field cmd, interrupt control field (e.g. “1” indicates generating an interrupt when the descriptor ends), BCC check mode BCC, transfer destination node Tgt, and transfer destination (Write Side) memory address DDA.
The second word is comprised of the number of transfer bytes SIZE (e.g. max. 1 Mbytes, min. 8 bytes), and transfer source (Read Side) memory address SDA. The third word is the Block-ID initial value for checking Check BKID, and the fourth word is the Block-ID initial value for generation (Replace).
The CPU 100 creates the descriptor shown in FIG. 10 each time data is written to the cache memory 104, and writes it in the descriptor area 106 in the cache memory 104. A memory area, which is N times the descriptor size, is allocated for the descriptor area 106.
The CPU 100 also writes the first address of the descriptor area 106 itself in the descriptor base address register 110 of the DMA engine 102 when DMA is started up. By this, the DMA engine 102 can know the address of the cache memory 104 from where the descriptor is written.
This DMA engine 102 has a descriptor top pointer register 112 and descriptor bottom pointer register 114. These registers 112 and 114 indicate the number of descriptor that the CPU 100 provided in the descriptor area 106, and the number of descriptors of which the DMA engine 102 ended execution respectively. In other words, the top register 112 indicates the first descriptor (descriptor #5 in FIG. 9), and the bottom register 114 indicates the last descriptor (descriptor #1 in FIG. 9).
A continuous space from the address indicated by the descriptor base address register 110 to N times of one descriptor size is used as the descriptor area 106. In the case of the example in FIG. 9, the CPU 100 creates six descriptors, #0-#5, and stores them in the descriptor area 106, then advances the value of the descriptor top pointer register 112 of the DMA engine 102 to “6”. By this, the DMA engine 102 knows that the descriptors are prepared, and starts reading the descriptors from the last descriptor (e.g. see Japanese Patent Application Laid-Open No. S63-211032, and Japanese Patent Application Laid-Open No. 2004-110159).
In other words, the DMA engine 102 reads the descriptor from the position indicated by the descriptor bottom pointer register 114 of the descriptor area 106, analyzes it, and increments the descriptor bottom pointer register 114 by “1” when the specified data transfer completes. FIG. 9, for example, shows the case that the descriptor bottom pointer register 114 is “1”, and that the processing of the descriptor #0 has already been completed.
The data itself has a check code to be guaranteed and the data of the cache memory also has an ECC (Error Check Code), and corruption of data due to an abnormality of the data path between the DRAM (Dynamic Random Access Memory) element and the memory controller and an abnormality of the DRAM which constitute the memory, can be detected.
In this way, data is protected by the above mentioned check code and the ECC in the data transfer operation by the DMA engine 102, but protection of the descriptors is not sufficient. In particular, the address during DMA transfer is not protected, so if a failure is generated in the address line between the memory controller and the memory, the CPU may write a descriptor to an incorrect address or the DMA engine may read a descriptor from an incorrect address.
In this case, data different from original data is DMA-transferred, and as a result data cannot be guaranteed.